In many integrated circuits there is the need to control numerous states. The chip interface is a module in the integrated circuit that translates the input conditions that are visible outside of the chip, to the selection of particular states within the chip that correspond to the deterministic state required. An example is that of a radio front end module that consists of a selection of switches, power amplifiers and low noise amplifiers. A setting of the input controls that relate to a receive or a transmit function, require that a set combination of switch settings and the enabling of the required amplifiers is accomplished.
In FIG. 1, the concept of the chip interface is shown. The master chip 101 is provided with the desired controls and the chip interface block 103 of chip 100 translates the input signals into a set of control logic signals that select the required modules (module-1 105, module-2 106 till module-N 109).
An example of a simple chip interface 110 is given in FIG. 2. FIG. 2 illustrates a simple chip interface where each input control is directly connected to a specific function within the chip. In this example, setting the control input CNTRL 0 to a 1 might relate to the enabling of the low noise amplifier (LNA 111) and setting the control CNTRL 1 to a zero might select the antenna switch 112 so as to connect the antenna to the input of the LNA. This would be the settings for the receive function and might correspond to also setting CNTRL 2 to a zero. Similarly, in order to select the transmit function CNTRL 0 will be a zero and CNTRL 1 a 1 so as to select the output of the power amplifier (PA 113) to the antenna. In this case, CNTRL 2 would be set to a 1 in order to enable the PA.
More common would be the case where the Control Block (such as control block 121 of FIG. 3) also contains a decoder. In our example above, we have just two states, receive and transmit. Table A below shows the required logic states of the three outputs in order to set up the desired states of receive or transmit. A decoder block (denoted decoder 122 in FIG. 3) translates the two control inputs into the required settings of the three output signals to control LNA 111, antenna switch 112 and PA 113. This is shown in FIG. 3.
TABLE ALogic Truth Table for Receive and Transmit statesEnable LNAAntenna SwitchEnable PAReceiveON (1)RX position (0)OFF (0)TransmitOFF (0)TX Position (1)ON (1)
In comparing FIGS. 1 and 2 it is seen that three input control pins is reduced to two. This can be expanded and it is common practice to decode a number of chip interfaces using a decoder block so as to reduce the number of pins required on the chip.
The challenge that arises when using a decoder block in order to reduce the pin count is that in many applications the time between the changes of the input state and the change of the output states must be low and also that any transient conditions of the output states must be avoided so as to not allow any illegal combinations even for a short time. In the example of a wireless front end module, the switching time between receive and transmit needs to be in the order of 10s of nanoseconds. The traditional method to achieve this fast change time is to use very high clock speeds in the order of 10s of MHz and this adds complexity, power consumption, chip area and noise to the system.
Other challenges must be met. When the input state is changing there can be a skew between the transition times of the various input signals and hence it is necessary to sample the new state only after the input states have stabilized. In order to avoid glitches in the output signals all the output signals must be changed at the same time so as to avoid illegal combinations.